Show HN: m6502, a 6502 CPU for FPGAs and Tiny Tapeout

A compact MOS 6502 CPU implementation in SystemVerilog, designed for FPGA and ASIC deployment with a focus on minimal gate count.

m6502 is a cycle-accurate 6502 CPU core that can be used standalone or integrated into larger systems. The core is optimized for resource-constrained environments, making it suitable for small FPGAs like the Lattice iCE40 (Fomu) and projects with limited I/O like Tiny Tapeout.

An optional MCU wrapper is provided as a practical way to experiment with the core, offering peripheral integration (GPIO, SK6812 LED controller) and simplified memory interfacing. However, the CPU core itself is fully standalone and can be integrated into any design.

The CPU core is a fully synthesizable implementation of the MOS 6502 processor. Key architectural decisions:

The MCU wrapper provides a complete microcontroller platform:

The design supports two primary memory configurations:

Block RAM (BRAM): Internal FPGA memory for program and data storage. Ideal for standalone applications where the entire program fits in on-chip RAM.

External Bus: Traditional 6502-style external memory interface with full 16-bit address and 8-bit data buses. Allows connection to external ROM, RAM, and memory-mapped peripherals like a real 6502 system.

For pin-constrained applications (such as Tiny Tapeout), an optional bus multiplexer reduces the required I/O pins from 24 (16 address + 8 data) to just 8 shared pins plus control signals.

The multiplexer operates in four phases:

An RP2040 PIO implementation provides external RAM/ROM using this multiplexed interface.

Note: Bus multiplexing is only necessary for platforms with limited pin count. Designs with sufficient I/O can use the full parallel bus interface directly.

Current peripheral implementations:

GPIO: 8-bit general-purpose I/O with pin multiplexing

SK6812 RGBW LED Controller: Hardware driver for SK6812 addressable LEDs

Timer: 16-bit timer with prescaler and interrupts

Clock Control: CPU clock frequency management

UART: Serial communication controller

See docs/peripherals.md for detailed peripheral documentation.

Minimal implementation targeting the Fomu USB board with iCE40UP5K FPGA. Demonstrates the design running in ~1000 LUTs with block RAM for program storage.

Development platform with more resources, used for testing and validation with external peripherals.

See docs/targets.md for build instructions and target-specific details.

This implementation prioritizes:

MIT